| Machine type | Shared-memory multi-vector processor. |
|---|---|
| Models | X1 (cluster). |
| Operating system | UNICOS (Cray Unix variant). |
| Connection structure | Crossbar. |
| Compilers | Fortran 90, C, C++, Co-Array Fortran, UPC. |
| Vendors information Web page | www.cray.com/products/systems/x1/ |
| Year of introduction | 2002. |
System parameters:
| Model | Cray X1 |
|---|---|
| Clock cycle | 800 MHz |
| Theor. peak performance | |
| Per Proc. (64 bits) | 3.2/12.8 Gflop/s |
| Maximal | 819 Gflop/s |
| Memory | <= 1 TB |
| No. of processors | 16--64 (MSP, see below) |
| Memory bandwidth | |
| Memory-Cache | 34.1 GB/s |
| Cache-CPU | 76.8 GB/s |
Remarks:
The hardware structure of the Cray X1 is almost identical to that of the Cray SV1ex. The clock frequency has been raised from 500 to 800 MHz and the amount of memory and the bandwidth to the processors are increased. Like on the SV1ex processors can run in Single Stream Processing (SSP) mode or Multi Stream Processing mode (see the remarks of the Cray SV1ex for an explanation). Only MSP mode now seems to be regarded as the standard and restriction in the configuration of SSP and MSP complexes does not apply anymore. This is also visible in the processor count given in the data sheets of Cray: the maximum number within one cabinet is 64 MSP processors. This is equivalent to 256 SSP processors. In the present Cray optimisation documentation it is said that the Cray Programming Environment is as yet not optimised for SSP processing which is not to say that suitable programs would not run efficiently in SSP mode.
The relative bandwidth both from memory to the CPU boards and from the cache to the CPUs has improved much in comparison to the SV1ex: from memory to the CPU board 5.3 8-byte operands can be transferred. From the cache the peak bandwidth to the CPUs is 12 8-byte operands, enough to sustain dyadic operations. The cache structure is rather complex each of the 4 SSPs on a board have their own 16 KB 2-way set-associative L1 data and instruction cache. The the L1 data cache only stores scalar data. The L2 cache is 2MB in size and is shared by the SSP processors on the CPU board.
New features that are less visible to the user are adherence to the IEEE 754 floating-point standard arithmetic and a new vector instruction set that can make better use of the new features like caches and addressability and synchronisation of remote nodes. This is because every cabinet can be regarded as a node in a cluster of which a maximum of 64 can be configured in a 3-D torus topology. Nowhere in the documentation the characteristics of this network is given, although one can surmise that the network technology as employed in the Cray T3E is also used here. Because of the lack of documentation latency and bandwidth of the network are unknown to the author as yet. On a 4-SSP CPU board OpenMP can be employed. When accessing other CPU boards one can use Cray's shmem library for one-sided communication, MPI, Co-Array Fortran, etc.
Measured Performances: The Cray X1 is still rather new, so not many performance results are available. In [38] a speed of 675.5 Gflop/s is reported for solving a 168,960-order linear system on a 60-(MSP)processor machine. This amounts to an efficiency of 88%.